一种高速LZW压缩算法FPGA硬件实现

A High Speed LZW Compression Algorithm Hardware Implementation Based on FPGA

在分析LZW算法的基础上,基于FPGA,设计了一个高速LZW压缩算法硬件加速电路,包含异步FIFO、状态机控制和双端口RAM三个主要部分。通过异步FIFO实现提高了数据传输速度;采用精简状态机模块提高了FPGA内部资源的利用率。在Kintex-7 XCKU060平台上验证了设计的正确性和加速特性。实验结果表明,数据压缩速率提升至366 Mbit/s,相比高性能通用处理器平台加速到9.1倍,能效比提升到65.5倍,可满足多种场景下实时无损压缩应用需求。

Based on the analysis of the LZW algorithm,a hardware acceleration circuit of high speed LZW compression algorithm was designed based on a FPGA,which included an asynchronous FIFO module,a state machine module and a dual-port RAM module.The asynchronous FIFO was used to improve the data transmission speed,and the simplified state machine module was used to improve the utilization of internal resources of the hardware platform.The correctness and acceleration characteristics of the design were verified on a Kintex-7 XCKU060 platform.The experimental results showed that the data compression speed was increased to nearly 366 Mbit/s,which was nearly 9.1 times faster than the high performance general purpose processor platform,and the energy efficiency ratio was increased by about 65.5 times.The system could meet the requirements of real-time lossless compression application in various scenarios.