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基于Verilog的双读数头光栅尺测量控制电路设计 被引量:2

Control Circuit Design of Linear Encoder Measuring with Double Reading Heads Based on Verilog
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摘要 为了达到低成本实现高精度大长度光栅尺测量的目的,笔者使用FPGA设计一个精度高、反应迅速的BiSS通讯的双读数头绝对式光栅尺测量控制电路。首先,通过对BiSS通讯协议原理与双读数头测量原理的研究,笔者在QUARTUS II软件开发平台上使用Verilog HDL语言来完成各个模块的描述、编译,然后在第三方仿真工具Modelsim中对其进行调试与模拟仿真实验。仿真实验结果证明,系统可实现100 kHz的传输速率,数据最大延时为41 ns,接收及计算数据正确,工作状态稳定、良好,达到了设计要求,实现了高精度大长度光栅尺测量的目标。 In order to achieve the goal of high precision and large length grating ruler measurement at low cost,a double reading head absolute grating ruler measurement and control circuit with high precision and quick response is designed by using FPGA.Firstly,through the research on the principle of BiSS communication protocol and double reading head measurement,the description and compilation of each module are completed by using Verilog HDL language on QUARTUS II software development platform.Finally,the debugging and simulation experiments are carried out in the third-party simulation tool Modelsim.The simulation results show that the system can realize the transmission rate of 100 kHz,the maximum delay of data is 41 ns,the receiving and calculating data are correct,the working state is stable and good,the design requirements are met,and the high precision and long grating ruler measurement is realized.
作者 黎家耀 王晗 姚洪辉 张嘉荣 曾景华 Li Jiayao;Wang Han;Yao Honghui;Zhang Jiarong;Zeng Jinghua(Faculty of Electrical and Mechanical Engineering,Guangdong University of Technology,Guangzhou Guangdong 510006,China)
出处 《信息与电脑》 2019年第24期82-85,共4页 Information & Computer
基金 广东省大学生科技创新培养专项基金(项目编号:PDJHB0160)
关键词 Verilog HDL 双读数头测量 BiSS通讯 QUARTUS II 13.1 MODELSIM VerilogHDL Measuring with double reading heads QUARTUS II 13.1 Modelsim
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