一种高性能低功耗的双节点翻转加固锁存器

HLDRL latch: a high performance, low cost, double node upset resilient latch

随着半导体工艺尺寸的发展,时钟频率越来越高,临界电荷变得越来越小,电路节点之间的电荷共享效应变得愈加严重,因此导致多节点翻转(multiple node upsets,MNU)的几率变大。为了解决MNU的问题,文章提出了一种高性能低功耗的双节点翻转加固锁存器(HLDRL),当受到单粒子效应影响时,具有单节点翻转(single node upset,SNU)和双节点翻转(double node upsets,DNU)的自恢复能力。该锁存器由18个异构输入反相器组成,仿真实验结果显示该锁存器具有优良的容错性能,可以实现DNU的完全自恢复,而且对高阻态不敏感。与其他容忍DNU的锁存器相比,该锁存器具有较小的开销,延迟和功耗延迟积分别减小了46.83%和45.85%。

With technology scaling and higher operating frequency, critical charge becomes smaller and charge sharing in circuit nodes significantly increases the probability of multiple node upsets(MNU). In order to solve the problem of MNU, this paper designs and proposes the HLDRL latch, which is a high performance, low cost, double node upset resilient latch. It has the single node upset(SNU) and double node upsets(DNU) resilient ability when it is affected by single event effect(SEE). The proposed latch is mainly composed of 18 heterogeneous-input inverter(HI) elements, which is evolved by traditional inverters. Extensive simulation results show that the proposed latch has the superior fault-tolerance performance. The latch can recover the previous state from SNU and DNU totally, and it is insensitive to high impedance state(HIS). Compared with other DNU tolerant latch, the proposed latch is cost-effective, and saves 46.83% in delay and 45.85% in power-delay-product(PDP) averagely.