高速数据压缩及加密硬件加速电路研究

High Performance Data Compression and Encryption Hardware

数据的爆炸式增长和有限的带宽使得数据压缩日渐重要,但是对于关键和敏感数据只是单纯地进行压缩会面临泄漏和窃听等信息安全风险,因此还需要对压缩后的数据进行加密。为解决软件压缩加密速度慢、占用大量CPU资源的缺点,论文实现了同时具有LZ4数据压缩模块和AES加密模块的FPGA硬件加速电路,并且修改了LZ4部分数据格式以适应硬件的运行,通过乒乓操作进一步优化了硬件的性能。在Vivado 2016.4中进行了Verilog代码的设计和仿真,然后在Xilinx KC705评估板上进行了实现和测试,最高实际测试频率达到了220MHz,流水线的设计使得吞吐率可达1760Mbps,性能超过了之前已有的最佳设计。

Data compression is becoming increasingly important due to the explosive growth of data and the limited bandwidth.However,the critical data that are simply compressed are facing information security risk.Therefore,it is required that the com pressed data should also be encrypted.In order to speed up the data compression and encryption,this paper studies the FPGA imple mentation of both LZ4 compression and AES encryption algorithms.The LZ4 data format has been modified for hardware implemen tation.The algorithms are designed using Verilog and simulated in Vivado 2016.4.The design is finally implemented on Xilinx Kin tex-7 KC705 evaluation board.The design can run up to 220MHz,w hich provides a throughput up to 1760Mbps.It is faster than all previous designs.