40 nm IC静态和动态ESD测试及失效分析

Static and Dynamic ESD Testing and Failure Analysis for 40 nm IC Products

结合电网内使用电子器件面临的复杂电磁环境,介绍芯片在静态和动态下静电放电(electrostatic discharge,ESD)的防护能力测试,分析了ESD器件充放电模式(CDM)失效的现象和定位方法.针对40 nm LQFP64封装芯片,详细介绍ESD测试过程和失效判定分析过程,综合运用激光束电阻异常侦测、扫描电子显微镜等手段完成对失效位置的定位和失效点的精确分析.通过测试结果分析其失效机理,ESD保护电路中的晶体管,在电阻率下降、电流密度增加导致温度升高的正反馈作用下保护电路中的晶体管发生熔断,从而导致ESD保护电路失效.

Considering the complex electromagnetic environment faced by the use of electronic devices in the power grid,the paper introduces the test of ESD protection ability under static and dynamic conditions. ESD charged device model(CDM)failure phenomenon and location method of failure position are analyzed. Based on LQFP64 package form IC,using 40 nm,the ESD test method and failure phenomenon determination process is discussed in detail. OBIRCH and SEM are used to locate the failure position and analyze the failure point accurately. Through the detailed test results,the failure mechanism of the transistors in the ESD protection circuit is analyzed. Under the positive feedback of the decrease of resistance and the increase of current density,the transistors in the protection circuit will fuse,which leads to the failure of the ESD protection circuit.