高线性度CMOS模拟乘法器设计与仿真

Design and simulation of high linearity CMOS analog multiplier

设计和仿真了一种高线性度CMOS模拟乘法器。采用有源衰减器对输入信号进行预处理,CMOS Gilbert乘法单元对信号进行乘法运算,同时设计了偏置电路。在±1.8 V电源电压下,输入范围为±0.6 V时,通过优化器件参数,乘法器输出幅度小于±25 mV且具有高线性度。乘法器-3 dB带宽为181 MHz,有着良好的倍频特性。此外,对乘法器的温度特性进行了仿真,讨论了线性度与输出幅度之间的关系,优化设计了乘法器版图。在较宽输入范围内,本文乘法器线性度明显高于参考文献。

A high linearity CMOS analog multiplier is designed and simulated.The input signal is preprocessed by active attenuator and the CMOS Gilbert multiplier is used for multiplication of the signal,and the bias circuit is designed meanwhile.When the supply voltage is±1.8 V and the input range is±0.6 V,the output range is less than±25 mV and good linearity of the analog multiplier is obtained using optimized characteristics of transistors.The frequency doubling character of the analog multiplier is favor-able since the-3 dB bandwidth of the analog multiplier is 181 MHz.Moreover,the temperature characteristic of multiplier is simu-lated and the layout of multiplier is designed optimally,and the relationship between linearity and output amplitude is discussed.The linearity of the multiplier during wider input range proposed herein is higher than that in the references.