混合基可重构FFT处理器的设计与实现

Design and implementation of mixed radix reconfigurable Fast Fourier Transform processor

本文提出了一种新型混合基可重构FFT处理器,由支持基-2/3FFT的新型可重构蝶形单元和多路并行无冲突的存储器组成,实现了FFT过程中多路数据并行性和操作的连续性.本设计在TSMC28nm工艺下的最高频率为1.06GHz,同时在Xilinx的XC7V2000T FPGA芯片上搭建了混合基FFT处理器硬件测试系统.对混合基FFT处理器的FPGA硬件测试结果表明,本设计支持基-2、基-3和基-2/3混合模式FFT变换,且执行速度达到给定蝶乘器数量下的理论周期值,对单精度浮点数,混合基FFT处理器可提供10-5的结果精度.

This paper presents a novel mixed radix reconfigurable FFT processor,which consists of a new reconfigurable butterfly unit supporting radix-2/3 FFT and multi-channel parallel collision-free memory,which implements multi-channel data parallelism and the continuity of the operation for FFT operation.The maximum frequency of this design is 1.06 GHz under the TSMC28 nm process.At the same time,the mixed radix FFT processor hardware test system based on the Xilinx’s XC7 V2000 T FPGA chip completes performance verification.The results shows that the design supports FFT operations for radix-2 mode,radix-3 mode and radix-2/3 mixed mode,and the execution speed reaches the theoretical period value under the given number of butterfly multipliers.For single-precision floating-point numbers,mixed radix FFT processor provides a result accuracy of 10-5.