期刊文献+

Architecture, challenges and applications of dynamic reconfigurable computing 被引量:4

Architecture, challenges and applications of dynamic reconfigurable computing
下载PDF
导出
摘要 As a computing paradigm that combines temporal and spatial computations,dynamic reconfigurable computing provides superiorities of flexibility,energy efficiency and area efficiency,attracting interest from both academia and industry.However,dynamic reconfigurable computing is not yet mature because of several unsolved problems.This work introduces the concept,architecture,and compilation techniques of dynamic reconfigurable computing.It also discusses the existing major challenges and points out its potential applications. As a computing paradigm that combines temporal and spatial computations, dynamic reconfigurable computing provides superiorities of flexibility, energy efficiency and area efficiency, attracting interest from both academia and industry.However, dynamic reconfigurable computing is not yet mature because of several unsolved problems. This work introduces the concept, architecture, and compilation techniques of dynamic reconfigurable computing. It also discusses the existing major challenges and points out its potential applications.
出处 《Journal of Semiconductors》 EI CAS CSCD 2020年第2期4-13,共10页 半导体学报(英文版)
基金 supported in part by the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2018ZX01028201) in part by the National Natural Science Foundation of China (Grant No. 61672317, No. 61834002) in part by the National Key R&D Program of China (Grant No. 2018YFB2202101)
关键词 reconfigurable computing ARCHITECTURE CHALLENGE APPLICATION reconfigurable computing architecture challenge application
  • 相关文献

参考文献2

二级参考文献25

  • 1Compton K, Hauck S. Reconfigurable computing: a survey of systems and software. ACM Comput Surv, 2002, 2: 171-210.
  • 2Banerjee S, Bozorgzadeh E, Dutt N D. Integrating physical constraints in HW-SW partitioning for architectures with partial dynamic reconfiguration. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2006, 14:1189-1202.
  • 3Suzuki M, Hasegawa Y, Tuan V M, et al. A cost-effective context memory structure for dynamically reconfigurable processors. In: International Conference on Parallel and Distributed Processing, Rhodes, 2006. 188-188.
  • 4Lodi A, Mucci C, Bocchi M, et al. A multi-context pipelined array for embedded systems. In: International Conference on Field Programmable Logic and Applications, Madrid, 2006. 1-8.
  • 5Sano T, Kato M, Tsutsumi S, et al. Instruction buffer mode for multi-context dynamically reconfigurable processors. In: International Conference on Field Programmable Logic and Applications, Heidelberg, 2008. 215-220.
  • 6Rossi D, Campi F, Spolzino S, et al. A heterogeneous digital signal processor for dynamically reconfigurable computing. IEEE J Solid-State Circuit, 2010, 45:1615-1626.
  • 7Shield J, Sutton P, Machanick P. Dynamic cache switching in reconfigurable embedded systems. In: International Conference on Field Programmable Logic and Applications, Amsterdam, 2007. 111- 116.
  • 8Huang J, Lee J H. A self-reconfigurable platform for scalable DCT computation using compressed partial bitstreams and blockRAM prefetching. IEEE Trans Circ Syst Video Technol, 2009, 19:1623-1632.
  • 9Kim Y, Mahapatra R N. Dynamic context compression for low-power coarse-grained reconfigurable architecture. IEEE Trans Very Large Scale Integr (VLSI) Svst, 2010, 18:15-28.
  • 10Dandalis A, Prasanna V K. Configuration compression for FPGA-based embedded systems. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2005, 13:1394-1398.

共引文献7

同被引文献35

引证文献4

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部