摘要
In order to accommodate the variety of algorithms with different performance in specific application and improve power efficiency,reconfigurable architecture has become an effective methodology in academia and industry.However,existing architectures suffer from performance bottleneck due to slow updating of contexts and inadequate flexibility.This paper presents an H-tree based reconfiguration mechanism(HRM)with Huffman-coding-like and mask addressing method in a homogeneous processing element(PE)array,which supports both programmable and data-driven modes.The proposed HRM can transfer reconfiguration instructions/contexts to a particular PE or associated PEs simultaneously in one clock cycle in unicast,multicast and broadcast mode,and shut down the unnecessary PE/PEs according to the current configuration.To verify the correctness and efficiency,we implement it in RTL synthesis and FPGA prototype.Compared to prior works,the experiment results show that the HRM has improved the work frequency by an average of 23.4%,increased the updating speed by 2×,and reduced the area by 36.9%;HRM can also power off the unnecessary PEs which reduced 51%of dynamic power dissipation in certain application configuration.Furthermore,in the data-driven mode,the system frequency can reach 214 MHz,which is 1.68×higher compared with the programmable mode.
In order to accommodate the variety of algorithms with different performance in specific application and improve power efficiency, reconfigurable architecture has become an effective methodology in academia and industry. However, existing architectures suffer from performance bottleneck due to slow updating of contexts and inadequate flexibility. This paper presents an H-tree based reconfiguration mechanism(HRM) with Huffman-coding-like and mask addressing method in a homogeneous processing element(PE) array, which supports both programmable and data-driven modes. The proposed HRM can transfer reconfiguration instructions/contexts to a particular PE or associated PEs simultaneously in one clock cycle in unicast,multicast and broadcast mode, and shut down the unnecessary PE/PEs according to the current configuration. To verify the correctness and efficiency, we implement it in RTL synthesis and FPGA prototype. Compared to prior works, the experiment results show that the HRM has improved the work frequency by an average of 23.4%, increased the updating speed by 2×, and reduced the area by 36.9%; HRM can also power off the unnecessary PEs which reduced 51% of dynamic power dissipation in certain application configuration. Furthermore, in the data-driven mode, the system frequency can reach 214 MHz, which is 1.68× higher compared with the programmable mode.
基金
supported by the National Natural Science Foundation of China (Nos. 61834005, 61602377, 61772417, 61802304, 61874087)
the Shaanxi International Science and Technology Cooperation Program No. 2018KW-006
Shaanxi Provincial Key R&D Plan under Grant No. 2017GY-060
Shaanxi Province Co-ordination Innovation Project of Science and Technology under Grant No. 2016KTZDGY02-04-02
