一种可重构以太网数据包解析器中可重构单元的设计

Reconfigurable unit design in a reconfigurable Ethernet packet parser

不停变化的网络协议标准和用户定制化网络业务需求要求交换机硬件具有更高的灵活性。在此背景下,提出了一种能够通过软件编程定义协议解析规则的以太网交换机芯片数据包解析器基本处理单元,具有高性能且高灵活性的优点,通过灵活配置硬件解析逻辑和查找表内容,定义对数据包包头内容的提取、查找、匹配、动作等解析过程,从而支持对不同种类的协议解析任务,其由2类基本结构的串联或并联组合而成,这样可以根据需要进行硬件资源裁剪。基于该可重构基本处理单元,可以构成可重构报文解析器,支持自定义协议及未知协议的解析。主要介绍了该可重构基本处理单元的结构,并介绍了基于该基本处理单元的解析器架构的实现方法。采用40 nm工艺综合后的评估结果显示,该基本单元电路最高工作时钟频率可以达到240 MHz,基于该基本处理单元结构实现的支持4层常用以太网协议解析的解析器每秒可处理2.4亿个数据包。该可重构基本处理单元所用存储资源共计87.98 Kb,设计规模约147万门。

The ever-changing network protocol standards and user-customized network services require greater flexibility for switch hardware.Under this background,this paper proposes a basic processing unit of an Ethernet switch chip packet parser,which can define protocol parsing rules by software programming and has the advantages of high performance and high flexibility.Hardware parsing logic and look-up table can be flexibly configured,and the extraction,search,match,action,and other parsing processes of packet header content are defined,so as to support different types of protocol parsing tasks.It is composed of two types of basic structures in series or parallel so that the hardware resources can be tailored according to the need.Based on the reconfigurable basic processing unit,the reconfigurable message parser can be constructed,which supports the parsing of custom protocol and unknown protocol.This paper mainly introduces the structure of the reconfigurable basic processing unit and introduces the implementation method of the parser architecture based on the basic processing unit.The synthesis results under 40nm process show that the maximum working clock frequency of the basic processing unit can reach 240MHz.Based on the basic processing unit,the parser,which supports the parsing of four-layer common Ethernet protocols,can process 240 million packets per second.The total storage resources used in the reconfigurable basic processing unit are 87.98K bit,and the design size is about 1.47 million gates.