应用于GNSS射频芯片的小数分频电路设计

Design of fractional frequency dividing circuits for GNSS RF chips

为了有效提高全球卫星导航系统(GNSS)的芯片性能,设计1种应用于GNSS射频芯片的小数分频器电路,能够实现16~255之间的小数分频:利用MASH1-1-1 Sigma-delta调制器的特性解决分频电路产生的小数杂散;并通过在调制器输入端加入1个由变形m序列产生的抖动电路,解决调制器的结构寄生问题;然后在ADS软件上针对GPS L1频点,以及4.092 MHz的中频信号与13、16.35、24.55 MHz外部参考频率之间不同的分频比,对调制器电路进行建模仿真;最后电路使用Verilog硬件语言设计实现,用Modelsim软件进行了功能仿真。仿真结果表明,小数分频器功能正确,且加入抖动后的调制器能够输出平滑、无毛刺的调制序列,能有效提高芯片性能。

In order to efficiently improve the chip performance of GNSS,the paper designed a decimal frequency divider circuit which can be applied in the RF chip of GNSS with the decimal frequency of 16~255:the fractional spur which is caused by prescale circuit was effectively solved by MASH1-1-1 Sigma-delta modulator;and a dither which is caused by the deformed m-sequence was added on the input of modulator to solve the problem of structure spuriousness;then modeling and simulation of the modulator circuit were carried out by ADS,which mainly aims to the different dividing rations between the GPS L1 frequency point,the IF signal of 4.092 MHz,and the frequency reference of 13,16.35 and 24.55 MHz;finally,the circuit was designed and implemented by Verilog hardware description language,and the functional simulation on Modelsim was done.Simulational result showed that the function of the decimal fraction frequency divider would be valid,and the modulator after adding the dither could output a smooth and burr-free modulation sequence for every occasion,which could effectively improve the performance of chips.