多层芯片键合界面的可靠性仿真分析

Reliability simulation analysis of multilayer chip bonding interface

为了提高芯片的集成度,采用三维堆叠,通过硅通孔(TSV)实现了芯片的垂直互联,能有效地增大集成度,采用键合技术实现三维集成互联,实现芯片的结构互联和电学互联,使用计算机模拟仿真键合工艺,可以有效地分析其可靠性并降低设计成本。通过COMSOL软件对双层芯片的键合工艺模拟仿真,并在工作温度下对可靠性进行分析。对两个含直径为14μm的TSV的芯片进行中间层为苯并环丁烯(BCB)的键合仿真。仿真结果表明:二层芯片所能承受的最大剪切力为20MPa,拉伸力为0.45 N,与常见的焊接结果一致。仿真结果可以在一定程度上模拟键合界面的可靠性。在此基础上,模拟了不同间距,不同焊盘大小、不同焊接材料下的键合区域可靠性情况,并通过对Von mesis应力的观察,发现焊盘距离为25μm时,焊接可靠性最好;铜锡共晶焊接在焊盘半径较大时,可靠性高于铜-铜直接焊接。

In order to increase chip integration,3D stacking is used.The vertical interconnection of chips is achieved,through through silicon vias(TSV),it can effectively increase the integration degree.Bonding is used to realize 3D integrated interconnection.The structural interconnection and electrical interconnection of the chip are realized.Reliability can be effectively analyzed and the design cost is reduced by using the computer simulation and simulation bonding process.Bonding process of the double-layer chip simulation is carried out by COMSOL software,and the reliability is analyzed at the working temperature.The intermediate layer is BCB for two chips with diameter of 14μm TSV.Bonding simulation of cyclobutene is carried out.Simulation results show that the maximum shear force that the two-layer chip can withstand is 20 MPa,and the tensile force is 0.45 N,which is consistent with common welding results.Simulation results can simulate the reliability of the bonding interface to some extent.On this basis,simulate the reliability of bonding areas under different pitches,different pad sizes and different solder materials,and observe the Von mesis stress and find that the soldering reliability is best when the pad distance is 25μm;tin eutectic soldering is more reliable than copper-copper direct soldering when the pad radius is large.