一种细粒度可重构的深度神经网络加速芯片

A Fine-Grained Reconfigurable Deep Neural Network Accelerating Chip

提出了一种高能效的细粒度可重构的深度神经网络(DNN)加速芯片。该芯片是基于并行计算阵列设计的,它包含144个处理单元,多个处理单元可以实现卷积、矩阵乘、取最大值或取平均值等运算,可以用于加速DNN。每个处理单元之间是通过片上网络(NOC)连接的,每个处理单元的运算结果可以直接发送给相邻的处理单元,运算中间数据不需要缓存。相邻处理单元间的数据流可以自由配置成各种拓扑结构,从而适配运算的多样性。为了实现激活函数,提出了一种高效的映射非线性函数的硬件实现方法。该芯片采用了标准的130 nm CMOS工艺制造,芯片面积为5.77 mm^2。该设计在133 MHz的工作频率下实现了38.3 GOPS的峰值算力。该芯片在1.2 V的电源电压下功耗为109 mW,芯片能效为0.351 TOPS/W。

A highly energy-efficient fine-grained reconfigurable deep neural network(DNN)acce-lerating chip was proposed.This chip was designed based on the parallel computing array.It consisted of 144 processing elements.Multiple processing elements can perform convolution,matrix multiplication,maximum pooling or average pooling,etc.,which can be used to accelerate DNN.Each processing element was connected through the network on chip(NOC).The results of each processing element can be sent directly to the adjacent processing element,and there was no need to cache intermediate data.The adjacent processing elements can be freely combined into a variety of topological structures,thus adapting to the diversity of operations.In order to realize the activating function,an efficient hardware implementation method for mapping the non-linear function was proposed.This chip was fabricated by standard 130 nm CMOS process with chip area of 5.77 mm^2.This design achieves a peak computing performance of 38.3 GOPS at 133 MHz.The power consumption of the chip is 109 mW at a supply voltage of 1.2 V,and the energy efficient is 0.351 TOPS/W.