一种卫星导航抗干扰处理器低功耗设计方法

A low-power design technique for GNSS anti-jam processor

提出一种适用于全球卫星导航系统(GNSS)智能天线的低功耗抗干扰处理器设计方法.通过改进GNSS抗干扰架构中混频器的设计,优化掉数字高中频混频器和滤波器.为进一步降低功耗和硬件资源占用,引入输出双倍速率寄存器(ODDR)技术,实现高中频信号的直接合成.实验测试结果表明,本设计功耗降低11%,硬件资源减少14%,可应用到GNSS智能天线系统中.

This paper presents a low-power anti-jamming processor for Global Navigation Satellite System(GNSS) smart antenna. By improving the design of mixer in GNSS anti-interference architecture, the digital high intermediate frequency mixer and filter are optimized. To further reduce the power consumption and resource occupation, an Output Double-Rate-Register(ODDR) scheme is introduced to realize the direct synthesis of high intermediate frequency signal. The experimental results show that the power consumption and hardware resources of this design are reduced by 11% and 14%, which can be applied to GNSS smart antenna system.