一种针对大规模CGRA的编译器后端设计

Design of Compiler Backend for Large-Scale CGRA

随着半导体工艺的飞速发展,粗粒度可重构架构(CGRA)上的处理单元数量日益增多,使得大规模CGRA出现异构访存结构以及有限互连资源设计,故传统CGRA编译器已经不再适配其新的架构特性。针对大规模CGRA设计一套新的编译器后端流程,其可以充分发挥CGRA的并行性。在搭建的RTL仿真环境中,通过测试一些典型计算密集型应用的运行时间,该编译器可以获得相对CPU平均76倍的应用加速比。

With the rapid development of semiconductor process,the number of processing units on coarse grained reconfigurable architecture(CGRA)is increasing,which makes the traditional CGRA compiler not adapted to its new architecture features,including the emergence of heterogeneous memory access structure and the limited interconnection resources between processing elements.In this paper,a new com piler back-end flow is designed for large-scale CGRA,which can give full play to the parallelism of CGRA.In RTL simulation,by testing the run time of some typical computing intensive applications,the compiler can achieve an average application acceleration ratio of 76 times compared with CPU.