自适应带宽锁相环建模分析与验证

Adaptive Bandwidth Phase-locked Loop Modeling Analysis and Verification

基于UMC 40 nm CMOS工艺,进行了自适应带宽锁相环的设计。根据自适应带宽锁相环原理和结构特点,对自适应带宽锁相环常用架构进行分析,并详细阐述自适应带宽锁相环系统模型。针对锁相环各模块引入噪声对输出信号噪声的贡献进行分析,并根据分析结果对其系统和噪声进行Matlab建模分析,最后通过测试验证了Matlab建模分析的结果。

The design of adaptive bandwidth phase-locked loop is based on UMC 40 nm CMOS process design,according to the of adaptive bandwidth phase-locked loop,and the characteristics of the structure architecture,which are used in the adaptive bandwidth phase-locked loop is analyzed,and expounds in detail the adaptive bandwidth phase-locked loop system model,in view of the phase-locked loop the contribution of each module is introduced into the output noise is analyzed.And according to the results of the analysis,the system analyzed Matlab modeling and noise,at last,verified the Matlab modeling by analysis results of test.