一种低掉电率的采样保持电路

A Sample-and-Hold Circuit with Low Droop Rate

设计了一种低掉电率、低功耗的采样保持电路。在电路保持阶段,将采样开关偏置在深积累区以减小亚阈值区电流,此时仍有源漏耦合电流,在采样开关源漏间加入高增益运算放大器,利用放大器的失调电压进行源漏耦合漏电补偿。考虑到失调电压的随机性,在采样开关源漏间并联一个体端偏置在高压的PMOS管以减小泄漏电流。此外,对栅压自举开关进行了改进,对于不同的输入信号,利用运算放大器和逻辑控制单元,得到恒定的导通电阻。采用Cadence Spectre软件的蒙特卡洛模型分别仿真了采样电路在-20,25和125℃下的掉电率,后仿真结果表明,室温下,在输入为0~2 V、采用±5 V电源供电时,采样保持电路掉电率为0.67 mV/s,捕获时间为3μs,采样开关导通电阻为1.5~2.5 kΩ,芯片面积为195μm×154μm,整体功耗为1.106 mW。

A sample-and-hold circuit with low droop rate and low power consumption was designed. During the hold phase, the sampling switch was biased in the deep accumulation region to reduce the current of sub-threshold region. Due to the source-drain coupling current still exists, a high-gain operational amplifier was inserted between the source and drain of the sampling switch to perform the source-drain coupling leakage compensation by using the offset voltage of the amplifier. Considering the randomness of the offset voltage, a PMOSFET which body biased at a high voltage was connected in parallel between the source and drain of the sampling switch to reduce the leakage current. In addition, the bootstrapped switch was improved. For different input signals, a constant on-resistance was obtained by using the operational amplifier and the logic control unit. The Monte Carlo model of Cadence Spectre software was used to simulate the output droop rate at-20, 25 and 125 ℃, respectively. The post-simulation results show that when the input is 0-2 V and the power supplies ±5 V at room temperature, the droop rate of the sample-and-hold circuit maintains 0.67 mV/s and the acquisition time is 3 μs, the on-resistance of the sampling switch is 1.5-2.5 kΩ. The chip area is 195 μm×154 μm and the overall power consumption is 1.106 mW.