一种基于热阻网络的叠层芯片结温预测模型

A Stacked Chip Junction Temperature Prediction Model Based on Thermal Resistance Network

提出了一种基于热阻网络的叠层芯片结温预测模型,该模型根据芯片内各组件的尺寸和热导率计算出对应的热阻,同时考虑了接触热阻和热量耦合效应,从而得到每层芯片在不同功耗情况下的结温预测值。在一个三芯片堆叠结构中,使用提出的方法对芯片结温进行预测,并与ANSYS仿真软件结果作比较,发现结温预测值的相对误差均小于4.5%。因此,该模型仅需根据芯片结构和材料参数,便可快速精确地估算出芯片在不同工作环境下的结温值。

A prediction model of junction temperature of stacked chip based on thermal resistance network is proposed.The model calculates the corresponding thermal resistance according to the size and thermal conductivity of each component in the chip,and considers the contact thermal resistance and heat coupling effect,and finally obtains the predicted junction temperature of each layer of the chip under different power consumption conditions.In a three-layer die structure,the junction temperature of the chip is predicted using the method proposed in this paper,and compared with the results of AN SYS simulation software,the relative error of the junction temperature prediction value is less than 4.5%.Therefore,the model can quickly and accurately estimate the junction temperature of the chip under different working conditions by knowing merely the structure and material parameters of the chip.