CPT铷原子钟锁相环频率合成器设计和分析

Design and Analysis of PLL Frequency Synthesizer for Rb Atomic Clock

基于CPT(相干布局囚禁)87铷原子钟设计出输出频率为3417 MHz的锁相环频率合成器,通过ADIsimPLL仿真出最佳环路带宽,环路滤波器参数以及相位噪声等,并通过STM32对锁相环芯片进行控制。对频率合成器进行了测试,电路尺寸为40 mm×40 mm,输出信号功率范围为-4 dBm^+5 dBm可调,输出信号噪声满足要求-88.65 dBc/Hz@1 kHz,-92.31 dBc/Hz@10 kHz,-104.63 dBc/Hz@100 kHz,杂散和谐波得到抑制,设计的频率合成器能很好的应用于原子钟的射频信号源。

A phase locked loop frequency synthesizer with an output frequency of 3417 MHz is designed based on CPT(Coherent Population Trapping)87 Rb atomic clock,ADIsimPLL is used to simulate the optimal loop bandwidth,loop filter parameters and phase noise,STM32 is used to control the PLL chip.The frequency synthesizer is tested,the circuit size is 40 mm×40 mm,the output signal power range is adjustable(-4 dBm^+5 dBm),the output signal noise meets the requirements-88.65 dBc/Hz@1 kHz,-92.31 dBc/Hz@10 kHz,-104.63 dBc/Hz@100 kHz,the spurious signals and harmonic are suppressed.The designed frequency synthesizer can be well applied to the RF signal source of atomic clock.