阵列处理器分布式Cache的局部优先访问结构设计

An intra-cluster local-priority efficient-access switch in distributed Cachee

针对可重构阵列处理器访存数据量大、数据并行性要求高且数据全局重用少、局部性明显的特点,提出了一种分布式Cache结构的簇内局部优先高效互连访问结构,该结构实现了簇内4×4个PE对4×4个Cache的并行访问,选用Xilinx公司的ZYNQ系列芯片XC7Z045 FFG900-2进行FPGA综合。在无冲突情况下,该互连结构支持簇内16个PE的同时读/写访问,最高频率可达221 MHz,访存峰值带宽为7.6 GB/s。在此结构上实现了灰度共生矩阵提取纹理图像特征算法,数据访存带宽达到478.125 MB/s,运行时间为0.24 ms。

Reconfigurable array processor has the characteristics of large amounts of memory data, high data parallelism, less global data reuse and obvious data locality. Aiming at these characteristics, this paper proposes an intra-cluster local-priority efficient-access switch in distributed Cache. The switch can make 4×4 PEs to access 4×4 Caches in parallel. Xilinx’s ZYNQ series chip XC7 Z045 FFG900-2 FPGA are used for FPGA synthesis. The switch can support the concurrent read and write operations of 16 intra-cluster PEs in the absence of conflicts, the working frequency can reach 221 MHz, and the memory bandwidth can attain 7.6 GB/s. The image texture extraction algorithm based on Gray-level Co-occurrence Matrix(GLCM) is implemented on this switch. The data memory bandwidth reaches 478.125 MB/s, and the execution time is 0.24 ms.