一种应用于SoC芯片的无片外电容LDO稳压器设计

Design of an output capacitor-less LDO regulator for SoC applications

基于0.18μm标准CMOS工艺,设计了一种应用于SoC芯片的无片外电容LDO稳压器电路。稳压器电路包括传统的LDO模块和瞬态增强辅助电路模块。源于LDO稳压器的工作原理以及如何增强误差放大器(EA)摆率的思想,提出一种新型的带开关电容瞬态增强电路。LDO稳压器的负载发生瞬态变化时,瞬态增强电路迅速响应,调整输出电压Vout。开关电容导通与关断时能够抑制Vout的跳变和缩短响应后建立时间,克服传统LDO稳压器Vout跳变与建立时间相互制约的缺陷。仿真结果表明:输入电压在1.8~5 V时,输出电压为1.8 V,线性调整率为0.122 mV/V,静态电流为45.3μA,负载阶跃从50μA到50 mA(反之亦然)的恢复时间均小于0.6μs,可满足SoC芯片的更高要求。

Design of an output capacitor-less LDO regulator is applied to SoC chip circuit. The circuit is fabricated in a 0.18μm standard CMOS process. The LDO regulator included a traditional LDO module and a transient enhanced auxiliary circuit module. Based on the principle of LDO regulator and the intention of increasing the error amplifier(EA)’s slew rate,a transient enhanced circuit with switched capacitor was proposed. When load current transients occur,the transient enhanced circuit responds quickly to adjust the output voltage Vout. The switched capacitor turn on and off can restrain the jump of Vout and shorten the response time,overcoming the restriction between the Vout jump and setup time of traditional LDO regulator. The simulation results show that the input voltage range is 1.8 V ~ 5 V and the output voltage is 1.8 V. The line regulation and quiescent current are 0.122 mV/V and 45.3 μA,respectively. The settling time is less than 0.6 μs for load steps from 50 μA to 50 mA(and vice versa).The performance can meet the higher requirements of SoC chip.