一种自时钟全数字LDO的设计

Design of a self clocking full digital LDO

利用VerilogA建模的方式实现了一种具有双向移位功能的自时钟数字LDO。该电路采用了粗糙和精细双环控制模块,其中利用双向移位寄存器产生自时钟;该模块与导通管部分的PMOS管阵列相结合,可以有效的减小输出电压的下溢或过冲,减少瞬态响应的时间。为了尽量减小输出电压的尖峰,利用电压阈值比较器和电压范围检测器,来确保双环的精确转换。介绍的数字LDO可以工作在0.8 V的低电源电压下,适用的负载电流可以大于260 mA,并且能够消除输出电容补偿的必要性。最后利用ADMS混仿平台,对建立的模型进行仿真验证。

A self clocking digital LDO with bidirectional shifting function is implemented by using VerilogA modeling.The circuit uses a coarse and fine dual loop control module,in which a self clock is generated by using a bidirectional shift register;the module is combined with the PMOS tube array of the conducting tube portion to effectively reduce the underflow or overshoot of the output voltage and reduce the transient response time.In order to minimize the spike in the output voltage,a voltage threshold comparator and a voltage range detector are used to ensure accurate conversion of the double loop.The digital LDO described can operate at a low supply voltage of 0.8V,with a suitable load current of more than 260mA,and eliminates the need for output capacitor compensation.Finally,using the ADMS mixed imitation platform,the established model is simulated and verified.