一种26~28 Gb/s高能效低抖动Bang-bang CDR设计

Design of a 26~28 Gb/s high power efficiency and low jitter Bang-bang CDR

设计实现了一款26~28 Gb/s的高能效低抖动Bang-bang CDR电路,采用改进的全速率非线性鉴相器结构,提高了鉴相器电路的输入灵敏度,改善高数据速率下磁滞效应的影响,从而提升环路整体的抖动性能;通过压控振荡器和压控振荡器缓冲电路协同调谐的方式减小为驱动大的鉴相器负载的时钟缓冲电路的功耗。采用TSMC 40 nm CMOS工艺,输入231-1300 mVPP的伪随机二进制序列(PRBS)数据,在28 Gb/s下该时钟数据恢复电路恢复出的时钟抖动为1.66 ps(pp),数据抖动为1.81 ps(pp);在注入4 MHz正弦抖动的情况下,抖动容限小于0.75 UIpp。在1 V电源电压下,功耗小于38.5 mW。

This paper presents a 26~28 Gb/s high power efficiency bang-bang CDR,an improved full-rate non-linear phase detector(PD)is adopted to improve the sensitivity of the input data and prevent the effect of hysteresis at high data rates,thereby improving the overall jitter performance of the loop.The co-tuning of VCO and VCO buffer is used to decrease the power consumption of the buffer to drive the heavy load of the PD.In 40 nm CMOS technology,the simulated recovered data jitter is 1.66 ps,the recovered clock jitter is 1.81 ps at 28 Gb/s for 231-1300 mVPP pseudo-random binary sequence(PRBS)as input data.The power consumption is less than 38.5 mW with 1 V supply.