一种基于Ring-VCO结构的宽频带低抖动锁相环的设计与实现

Design and implement of a ring-VCO based PLL with wide frequency range and low jitter

为了在高速传输系统中实现宽频带和低抖动时钟输出的要求,设计了一种基于Ring-VCO结构的低抖动锁相环,采用与锁相环锁定频率强相关的环路带宽调整方法来降低环路噪声,加速环路锁定,即利用全局参考调节电路中比较器模块将锁定控制电压与参考电压比较来改变各模块电流,根据不同锁定频率调整环路参数,大大缩短了锁定时间,同时利用四级差分环形振荡器和占空比调整电路的差分对称结构,降低了电路噪声。电路采用40 nm CMOS工艺实现,测试结果表明输出频率为1.0625 GHz^5 GHz,在最高时钟频率5 GHz下眼图质量良好,时钟抖动39.6 ps。

A ring-VCO based phase lock loop(PLL)is designed for achieving the wide frequency range and low jitter requirements of high speed communication system.By adjusting the loop bandwidth which is closely related to the lock-in frequency it reduces the loop noise and accelerates loop locking.Adopting the comparator in reference circuit to compare the locking control voltage with the reference voltage to flexibly change the current in other module,and adjusting the loop parameters according to different lock-in frequencies,the lock-in time is greatly reduced.At the same time,the differential symmetrical structure of the four-stage differential ring oscillator and duty cycle adjusting circuit is used to reduce the circuit noise.This chip is fabricated in 40 nm CMOS process,the measured results show that the output frequency is from 1.0625 GHz to 5 GHz,the performance of the signal at 5 GHz is good and jitter is 39.6 ps.