基于乘法器复用的信道化接收机的设计与应用

Design and application of channelized receiver based on multiplier reuse

针对广播频段信道数量较多、信道带宽较窄的场景,给出一种基于乘法器复用的信道化接收机的高效FPGA实现方案,并详细说明了信道化处理模块。方案采用流水线结构,复用较少的乘法器,完成所有信道的信道化处理,解决了信道数量众多时乘法器使用过多的问题。不仅能够保证处理的实时性,还大大减少了信道化接收算法硬件实现中的关键资源。最后通过硬件仿真,验证了该信道化处理模块仅需要复用8个复数乘法器IP核即可完成128个信道的多相滤波。例化并使用2个信道化处理模块即可完成广播频段的信道化处理,并运行在102.4 MHz的系统时钟频率下。

For the fact that the broadcasting band has more channels and narrow channel bandwidth,an efficient FPGA implementation scheme of channelized receiver based on multiplier reuse is proposed. The channelized processing module is elaborated. In the scheme,pipeline architecture is adopted and fewer multipliers are reused to complete the channelization of all channels,which solves the problem of requiring too many multipliers when there are a large number of channels. The scheme can not only guarantee real-time processing,but also greatly reduces application of the key resources during the hardware implementation when using the channelized receiving algorithm. It is verified by hardware simulation that the channelized processing module only needs to reuse 8 complex multiplier IP cores to complete polyphase filtering of 128 channels. The channelization of broadcasting band can be achieved by instantiating and using two channelized processing modules,and the channelized processing module can operate at the system clock frequency of 102.4 MHz.