基于GaAs HBT工艺的低相位噪声锁相环

Low Phase Noise Phase-Locked Loop Based on GaAs HBT Technology

设计了一款低相位噪声的锁相环(PLL),该PLL主要由可编程分频器、鉴相器和锁定指示电路等组成,通过外接参考时钟、有源环路滤波器和压控振荡器(VCO)构成完整的PLL频率源。研究了PLL频率源中各个噪声源及其传递函数,通过降低可编程分频器的相位噪声和提高鉴相器工作频率的方法,降低PLL频率源环路内的相位噪声。采用GaAs异质结双极晶体管(HBT)工艺对PLL进行了设计、仿真和流片,PLL芯片面积为1.95 mm×1.95 mm。测试结果表明,在电源电压5 V条件下,该PLL电流为250 mA,射频输入频率为0.01~2.2 GHz,鉴相器工作频率为0.01~1 GHz,分频比为2~32,典型归一化本底噪声为-232 dBc/Hz;当VCO输出频率为6 GHz,鉴相频率为500 MHz时,PLL频率源的相位噪声为-121 dBc/Hz@10 kHz。

A phase-locked loop(PLL) with low phase noise was designed. The PLL was mainly composed of the programmable frequency divider, phase detector and lock detect circuits. A complete PLL frequency source was composed of the external reference clock, active loop filter and voltage-controlled oscillator(VCO). The noise sources and their transfer function in the PLL frequency source were studied. The phase noise in the PLL frequency source loop was reduced by reducing the phase noise of the programmable frequency divider and increasing the operating frequency of the phase detector. The PLL chip with an area of 1.95 mm×1.95 mm was designed, simulated and fabricated with GaAs heterojunction bipolar transistor(HBT)technology. The test results show that under the supply voltage of 5 V, the PLL current is 250 mA, the RF input frequency is 0.01-2.2 GHz, the operating frequency of the phase detector is 0.01-1 GHz, the frequency division ratio is 2-32, and the typical normalized phase noise floor is-232 dBc/Hz. When the output frequency of VCO is 6 GHz and the phase detection frequency is 500 MHz, the phase noise of PLL frequency source is-121 dBc/Hz@10 kHz.