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评价功率VDMOS器件SEB效应的畸变NPN模型

A Distortion NPN Model for Evaluating SEB Effect of Power VDMOS
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摘要 构建了一个半径为0.05μm的圆柱体,用于模拟单粒子辐射功率VDMOS器件的粒子径迹,且圆柱体内新生电子和新生空穴的数目沿圆柱体的半径方向呈高斯分布。考虑到功率VDMOS器件的SEB效应与寄生NPN具有直接关系,提出了一种畸变NPN模型,并通过合理假设,推导出功率VDMOS器件在单粒子辐射下安全漏源偏置电压的解析式。结果表明,使用解析式计算得到的SEB阈值与TCAD仿真结果吻合较好。该模型可被广泛用于功率VDMOS器件SEB效应的分析和评价,为抗辐射功率VDMOS器件的选型及评价提供了一种简单和廉价的方法。 A cylinder with a radius of 0.05 μm was used to simulate the particle track of single event radiation in power VDMOS devices, and the number of newborn electrons and holes produced by radiation in the cylinder had distributed in accordance with Gauss distribution along the radius direction. Because the SEB effect of power VDMOS devices was directly related to parasitic NPN transistors, a distorted NPN model was proposed, and an analytical expression of the safe drain bias voltage of power VDMOS devices under single particle radiation was derived by reasonable assumptions. The results showed that the SEB threshold calculated by the proposed expression was in good agreement with the TCAD simulation results. The model could be widely used in the analysis and evaluation of SEB effect of power VDMOS devices. It provided a simple and inexpensive method for the selection and evaluation of radiation hardened power VDMOS devices.
作者 冯筱佳 唐昭焕 杨发顺 马奎 FENG Xiaojia;TANG Zhaohuan;YANG Fashun;MA Kui(Chongqing College of Electronic Engineering,Chongqing 401331,P.R.China;The 24th Research Institute of China Electronics Technology Group Corp.,Chongqing 400060,P.R.China;College of Big Data and Information Engineering,Guizhou University,Guiyang550025,P.R.China)
出处 《微电子学》 CAS 北大核心 2020年第2期236-240,共5页 Microelectronics
基金 空间环境材料行为及评价技术重点实验室资助项目(61429100306) 教育部工程研究中心资助项目(010201)。
关键词 功率VDMOS器件 单粒子烧毁 畸变NPN模型 耗尽区电场 power VDMOS single event burnout distortion NPN model electric field in depletion region
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  • 1Yilmaz H,Tsui T, Bencuya I,et al.Safe Operating Area of Power DMOS FETs[J].IEEE 1989 :173-175.
  • 2Ronghua zhu, Paul Chow T.A Comparative Study of the Quasi-saturation in the High Voltage Vertical DMOS for Different cell Geometries[C].Proceedings of 1998 international Symposi μm on Power Semiconductor Device & Ics,Kyoto:343-346.
  • 3Kuntjoro Pinardi, Ulrich Heinle. High-Power SOI Vertical DMOS Transistors With Lateral Drain Contacts: Process Developments,Characterization, and Modeling[J].IEEE Transactions on Electron Devices, 2004,51(5).

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