面向替换延迟隐藏的Cache空间预约技术

Hiding Cache Replacing Latency using a Cache Space Pre- ordering

快速发展的集成电路制造工艺与相对滞后的设计技术形成的"存储墙"问题已经成为制约限制处理器潜在性能提升的主要障碍,构建高性能片上存储系统一直是处理器微体系结构研究的重要内容。提出Cache空间预约技术--CSPO,为片上Cache增加预约空间计数器POC,以及Cache行预约标志POT,使Cache替换目标选择与片外存储器访问并行执行,同时具备将POT标识为1的脏Cache数据行尽快提前写回的能力,从而在片外数据返回前提前完成Cache替换目标行选择和脏数据写回,并将替换目标Cache行地址存入专用寄存器中,数据返回后直接写入替换目标Cache行,从而有效隐藏Cache替换操作延迟、提升IPC。实验结果表明,CSPO技术能有效提升IPC性能,范围为2.46%~11.11%,平均为5.37%。

The scissors difference between rapid progress of semiconductor fabrication and lagged development of design ability makes memory wall become the chief obstacle to dig the potential processor performance.So,how to construct on-chip high performance memory system is always one of the most important research content in processor architecture design.This paper proposes a Cache Space Pre-ordering technique,called CSPO.A pre-ordering space counter(POC) and Cache line pre-ordering tag(POT) is added to on-chip Cache,which make the processes of selecting of Cache replacement target line and the main memory accessing can be managed simultaneously,at the same time,dirty Cache line marked POT with 1 can be wrote back in advance as soon as possible.In general,the selection of Cache replacement target line can be done before the off-chip data returns.Further more,the selected object Cache line address is stored in Cache pre-ordering address register(CPAR),which can be used directly by the off-chip returned data for Cache upgrading.As a result,the latency of Cache replacement is hiding,and the IPC is increased consequently.Simulation result indicates that,relative to the baseline architecture,CSPO technique improves IPC from 2.46% to 11.11%,averagely 5.37%.