高精度低噪声的低压差线性稳压器设计

Design of a Low Dropout Linear Voltage Regulator with High Precision and Low Noise

为提高电子产品供电性能,设计了一款具有高电源抑制比(PSRR)、超低静态电流、宽输入电压范围的低压差(LDO)线性稳压器。该电路采用预调节和噪声抵消技术,利用Cadence工具SMIC 0.35μm CMOS工艺,完成了整体电路的设计与仿真,并进行了流片。仿真结果显示,LDO线性稳压器输出线性调整率为0.05%/V,负载调整率为5.5%,温度系数为1.8×10^-5/℃;10 GHz带宽以内的电源抑制比在低频下能达到98 dB,静态电流最高仅为32μA。测试结果表明,芯片可以在3.3~40 V电源电压下正常工作,输出电压为3.3或5 V,最大负载电流为150 mA,可应用于USB和便携电子产品等多种设备。

To improve the power supply performance of electronic products, a low dropout(LDO) linear voltage regulator with high power rejection ratio(PSRR), ultra-low quiescent current and wide input voltage range was designed. The design and simulation of the overall circuit were completed by using the technology of pre-adjustment and noise cancellation with the Cadence tool and SMIC 0.35 μm CMOS process, and the chip was fabricated. The simulation results show that the output linear regulation rate of the LDO linear voltage regulator is 0.05%/V, the load regulation rate is 5.5%, and the temperature coefficient is 1.8×10^-5/℃. The PSRR within 10 GHz bandwidth can reach 98 dB at low frequency, and the maximum quiescent current is only 32 μA. The test results show that the chip can operate normally under the power supply voltage of 3.3-40 V, the output voltage is 3.3 or 5 V, and the maximum load current is 150 mA, which can be applied to USB, portable electronic products and other devices.