GPU-Based Non-Binary LDPC Decoder with Weighted Bit-Reliability Based Algorithm

In this paper, we present a graphics processing unit(GPU)-based implementation of a weighted bit-reliability based(w BRB) decoder for non-binary LDPC(NB-LDPC) codes. To achieve coalesced memory accesses, an efficient data structure for the w BRB algorithm is proposed. Based on the Single-Instruction Multiple-Threads(SIMT) programming model, a novel mapping strategy with high intra-frame parallelism is presented to improve the latency and throughput performance. Moreover, by using Single-Instruction Multiple-Data(SIMD) intrinsics, four 8-bit message elements are packed into a 32-bit unit and simultaneously processed. Experimental results show that the proposed w BRB decoder provides good tradeoff between error performance and throughput for the codes with relatively large column degrees or high rates.