摘要
为了提高铁路信号安全协议RSSP-Ⅱ中消息鉴定安全层消息认证码算法的安全性和实时性,首先将传统的MASL-TDES-MAC算法底层的加密算法改进为安全性能更强的高级加密标准AES算法,并对改进后的MASL-AES-MAC算法采用FPGA技术进行硬件设计,其次根据硬件设计所达到的最高时钟频率和逻辑资源消耗情况,对算法的硬件实现环节采用查找表技术和流水线技术进行优化,最后在QuartusⅡ软件和Modelsim软件上进行联合仿真实验。研究结果表明:经过改进及优化后的算法具有更高的最高时钟频率和更低的逻辑资源消耗,不仅提高了协议的安全性,而且改进及优化后的算法在实时性方面比原算法提高了69.84%。
The purpose of this paper is to improve the safety and real-time performance of the message authentication code algorithm in Railway Signal Safety Protocol-II(RSSP-II). The research method is firstly to improve the underlying encryption algorithm of the traditional MASL-TDES-MAC algorithm into the Advanced Encryption Standard(AES) algorithm with stronger safety performance, and then to implement hardware design of the improved MASL-AES-MAC algorithm by adopting FPGA technology. Secondly, according to the highest clock frequency and logic resource consumption achieved by hardware design, the hardware implementation of the algorithm is optimized by using Lookup Table technology and pipeline technology. Finally, Quartus II software and Modelsim software are used for joint simulation experiments. The results show that the improved and optimized algorithm has higher maximum clock frequency and lower logic resource consumption, which not only improves protocol safety, but also improves real-time performance by 69.84% compared with the original algorithm.
作者
张凯
伍忠东
刘菲菲
ZHANG Kai;WU Zhongdong;LIU Feifei(School of Electronics and Information Engineering,Lanzhou Jiaotong University,Lanzhou 730070,China)
出处
《铁道标准设计》
北大核心
2020年第5期181-189,共9页
Railway Standard Design
基金
中国铁路总公司科技研究开发计划重大课题(2017X013-A)。
关键词
铁路信号安全协议-Ⅱ
消息认证码算法
高级加密标准算法
FPGA技术
最高时钟频率
逻辑资源消耗
railway signal safety protocol-ii
message authentication code algorithm
advanced encryption standard algorithm
FPGA technology
maximum clock frequency
logic resource consumption