面向空间辐照环境的星载高速数字接口芯片设计方法

A Design Approach of Satellite High-Speed Digital Interface Chips for Space Radiation Environment

针对空间应用的高速串行接口芯片易受单粒子辐照而出现误码的问题,提出了一种面向空间辐照环境的星载高速数字接口芯片设计方法。首先,针对空间辐照诱发单比特错误导致高速串行接口传输出错问题,计算辐照时的高速串行接口误码率最劣值;然后,通过误码率最劣值计算出辐照环境下高速串行接口无误码传输所需的增益;最后,采用叠加编码增益及辐照干扰的高速串行接口链路评价模型,计算出高速串行接口物理编码子层(PCS)中不同编码方式的编码增益,并评估编码增益对辐照降低高速串行接口误码率的补偿效果,根据补偿效果选择RS-8B/10B级联编码作为PCS编码。采用该高速数字接口芯片设计方法设计了一款速率为3.125 Gb/s的抗辐照高速串行接口芯片,其面积为4.84 mm^2,典型功耗为207 mW。单粒子辐照试验结果表明,对比传统设计方法,新的设计方法将芯片的单比特错误阈值提升了9 MeV·cm^2/mg。

A design approach for high-speed digital interface in satellite under space radiation is proposed to solve the problem that high-speed serial interface chips for space applications are susceptible to single-particle radiation.Firstly,the worst bit error rate(BER)of the high-speed serial interface is calculated over the issue of transmission error resulting in single bit error induced by space radiation.The gain required by zero-bit-error transmission in the radiation environment is deduced based on the worst BER;and then the coding gain for variable coding schemes in physical coding sub-layer(PCS)of the high-speed serial interface is inferred by using the link evaluation model featured with superposed coding gain and radiation interference.Meanwhile,the compensation effect of coding gain to BER degradation induced by radiation is evaluated,RS-8B/10B cascade coding is selected as the PCS coding according to the compensation effect.Finally,a 3.125-Gb/s radiation-hardened high-speed serial interface chip is designed using this design approach,and the chip occupies 4.84 mm^2 chip area and consumes 207 mW typical power.Experimental results with single-particle radiation show that the single-bit error radiation threshold for the proposed design approach scheme is 9 MeV·cm^2/mg higher than that for the traditional design approach scheme.