基于STT-MRAM的位逻辑运算方案及灵敏放大器设计

Bit logic operation scheme and sense amplifier design based on STT-MRAM

基于1T1MTJ的自旋转移矩-磁随机存储器(STT-MRAM)提出了一种改进型存内位逻辑计算方案。该方案通过精简2T2MTJ存内位逻辑运算方案提升了存储阵列密度,通过互补型读出电路增加了“与非”和“或非”的运算功能。此外,还通过增加支路电压稳定电路的方法,提出了一种适用于上述方案的改进型高速灵敏放大器。基于中芯国际55 nm LL逻辑工艺的仿真结果表明,相较于传统的灵敏放大器,该方案不仅读取速度提升了33%,在适配大型存储阵列(CB≥0.8 pF)时还拥有更强的读取能力与更优的功率积(PDP)。

Based on the spin transfer torque-magnetic random access memory of 1T1MTJ,an improved bit logic operation scheme in the memory is proposed in this paper.This scheme improves the storage array density by simplifying the 2T2MTJ bit logic operation scheme in the memory and increases the operation functions of"NAND"and"NOR"through the complementary readout circuit.In addition,an improved high-speed sense amplifier suitable for the above scheme is proposed by adding a branch voltage stabilizing circuit.Simulation results based on 55 nm LL logic process of SMIC show that,compared with traditional sense amplifiers,this scheme not only improves the reading speed by 33%,but also has stronger reading ability and better PDP when it is suitable for large storage arrays(CB≥0.8 pF).