一种基于CRPR的最大时钟偏差计算与定位算法

A Fast Algorithm of Calculating and Locating Max Clock Skew Based on CRPR

在超大规模集成电路中,不计其数的寄存器等基本时序单元通过时钟信号的控制以稳定的步调捕获和发送信号,支撑电路正确地运行。时钟树的设计和分析成为物理综合和静态时序分析中的关键环节,影响时序收敛的速度和最终的性能。提出一种基于CRPR的算法,能够精确和快速地定位最大时钟偏差,帮助物理综合优化程序或者设计者实现快速时序收敛。此算法的复杂度为O(n),即与基本时序器件的数量成线性关系。完成计算的同时定位最大偏差,以极低的成本反馈时序分析结果。

In VLSI,tremendous amount of registers and other sequential elements are controlled by clock signals to launch and capture normal digital signals at given pace,making it elementary for a chip to function as expected.Clock tree synthesis and optimization plays a critical role in the physical synthesis and static timing analysis(STA),timing closure and circuit performance are bounded by the quality.This paper presents a CRPR based algorithm,fast and accurate,on calculating and locating how much and where is the worst clock skew,which will favor the timing closure.This algorithm exposes O(n)complexity,linear to the number of sequential cells,with significantly low costs.