一种用于JESD204B协议的8B/10B并行编码电路设计与实现

Design and implementation of 8B/10B parallel coding circuit for JESD204B protocol

本文设计并实现了一种四路并行的8B/10B编码电路,通过了NCVerilog仿真验证,在某65nm工艺库下工作频率可达405MHz,可支持16.2Gbps的串行数据传输速率,占用逻辑资源面积1832μm^2,并作为JESD204B协议中的8B/10B编码模块已应用于某高速ADC芯片的SerDes接口电路中.经实际电路测试,本设计达到了JESD204B协议标准的12.5Gbps最高传输速率要求.

This paper designs and implements a four-way parallel 8B/10Bencoding circuit,which has been verified by NCVerilog simulation.It can work at 405MHz under a 65-nm technology library,supporting 16.2Gbps serial data transmission rate,occupying 1832μm^2 of logical resources.As the 8B/10Bcoding module in JESD204B protocol,it has been applied in the SerDes interface circuit of a high-speed ADC chip.The actual circuit test shows that the encoder meets the 12.5Gbps maximum transmission rate requirement of JESD204Bprotocol standard.