GaN HEMT栅工艺优化及性能提升

Performance improvements through gate process optimization for GaN HEMTs

针对0.5μm氮化镓高电子迁移率晶体管(GaN HEMT)自对准T型栅工艺,提出一种优化的解决方案。在感应耦合等离子体设备中引入两段法完成氮化硅栅足的干法刻蚀,其中,主刻蚀部分形成具备一定倾斜角度的氮化硅斜面,从而减小栅下沟道电场强度并提高栅金属对氮化硅槽填充的完整性;软着陆部分则以极低的偏置功率对氮化硅进行过刻蚀,确保完全清除氮化硅的同时尽量减小沟道损伤。通过器件优化前后各项特性的测试结果对比发现:优化后的器件关态击穿电压从140 V提升至200 V以上,3.5 GHz下输出功率密度从5.8 W/mm提升至8.7 W/mm,功率附加效率(PAE)从55.5%提升至66.7%。无偏置高加速应力试验96 h后,工艺优化后的器件外观无明显变化,最大电流变化<5%,表明器件可靠性良好。

Two-step dry etch method in the Inductive Coupled Plasma(ICP) chamber is proposed and applied to the SiN gate foot definition during the self-aligned 0.5 micron T-gate fabrication for GaN High Electron Mobility Transistor(GaN HEMT). The main etching part forms a tilted silicon nitride side wall, which reduces the electric field intensity in the channel under the gate and improves the gate metal filling in the silicon nitride recess. The soft landing part performs the over-etching process with a very low bias power to ensure the complete removal of silicon nitride and reduce the channel damage. Compared with the control device without any optimization, the off-state breakdown voltage of the optimized device shows an obvious increase from 140 V to more than 200 V. Moreover, the output power density and the Power Added Efficiency(PAE) at 3.5 GHz are promoted from 5.8 W/mm to 8.7 W/mm and 55.5% to 66.7%, respectively. After un-biased highly accelerated stress test for 96 hours, no obvious change in the appearance of the optimized device can be observed, and the change of the maximum drain current is less than 5%, indicating that the device reliability is pretty good.