面向宇航应用的高可靠SoC异常处理系统设计

Design of Exception Handling System for High Reliable System-on-Chip for Aerospace Applications

实现了面向宇航应用的高可靠SoC异常处理系统软硬件设计.为提高可靠性,将处理器及异常处理系统寄存器进行冗余设计,对SoC片上SRAM及各外设存储模块引入EDAC检错/纠错(纠一检二)机制.采用中断控制器统一管理众多的外设中断请求,对数据/指令的EDAC校验一位错和二位错异常,引入不同的硬件处理机制.一位错可通过EDAC逻辑纠正,不影响处理器正常运行,通过中断控制器以异步异常方式处理;二位错不能被EDAC逻辑纠正,影响处理器指令执行,通过总线反馈信号以精确同步异常方式处理,保证了异常响应的效率和系统可靠性.仿真验证结果表明,该异常处理系统可正确处理SoC众多外设和处理器内部异常.本文中的设计方法对高可靠处理器异常处理系统设计具有一定的参考价值.

An exception handling system is designed based on a high reliable system-on-chip for aerospace applications.Key registers of CPU and the exception processing system are designed using triple modular redundancy(redundancy)method to improve reliability.Furthermore,error detection and correction(EDAC)method is used for on-chip-SRAM and other memory modules.Interrupt controller(IC)is used to handle numerous peripheral interrupt requests.Different hardware processing mechanism is introduced to handle single error and two-bit error exception.Since single error can be corrected by EDAC logic and do not affect the normal operation of the processor,it is handled by IC in asynchronous exception mode.While the two-bit error cannot be corrected by EDAC logic and affects the instruction execution,two-bit error exception is passed to the processor through the bus response signal and handled as a precise synchronous exception.Simulation results show that the exception handling system can handle different peripheral interrupts and the internal exceptions of the processor efficiently and reliably.The design method reported in this paper has certain reference value for the design of high reliability processor exception handling system.