分数阶简化Lorenz系统的FPGA实现

FPGA Implementation of the Fractional-Order Simplified Lorenz System

目前针对分数阶混沌系统的研究大多数都是基于DSP(Digital Signal Processor)平台,由于分数阶混沌系统的复杂度较大,用DSP实现存在序列生成速度较慢的问题,只能应用于对速度要求不高的系统.针对该问题,研究了基于分数阶微积分Grunwald-Letnikov(GL)定义的分数阶简化Lorenz系统的FPGA(field programmable gate array)实现.通过最大Lyapunov指数和0~1测试验证了基于GL定义的分数阶简化Lorenz系统是混沌的.详细分析了基于GL定义的分数阶简化Lorenz系统的FPGA实现结构,并使用定点数格式实现了该系统.通过示波器观察FPGA输出结果与MATLAB仿真结果一致,从而进一步揭示了分数阶混沌系统的可实现性.

At present,most of the researches on fractional-order chaotic systems are based on the DSP platform.However,due to the complexity of fractional-order chaotic systems,the implementation of DSP has the problem of slow sequence generation,so that it can only be applied to low-speed systems.To solve this problem,an FPGA(field programmable gate array)implementation of fractional-order simplified Lorenz system based on the definition of fractional-order differential Grunwald-Letnikov(GL)is studied and developed.Firstly,it is verified through the maximum Lyapunov exponent and the 0-1 test that the fractional-order simplified Lorenz system based on the GL definition is chaotic.Then,the FPGA implementation structure of the fractional-order simplified Lorenz system based on GL definition is analyzed in detail,and the system is implemented using a fixed-point number format.Finally,the FPGA output results observed through an oscilloscope are shown to be consistent with MATLAB simulation results,which further reveals the feasibility of the fractional-order chaotic system.