Midori密码算法FPGA优化研究

Research on FPGA Optimization of Midori

基于SPN结构的分组密码Midori是以优化能耗为目的研发的一种应用于资源受限环境的轻量级分组密码。文章对Midori64算法的加密结构进行了优化,并以优化Midori64加密算法面积和提高部件复用率为目的提出了新的基于迭代的硬件体系结构。该结构将白化密钥加和轮密钥加进行了整合,通过多路复用器来完成白化密钥加变换或者轮密钥加变换。综合实验结果表明,基于新的硬件体系结构的Midori64加密算法在资源面积上少了100个LUTS,优化效率达到了26.25%,有效节省了硬件实现面积,同时加密速度提高了20.53%,能耗减少了17.15%。

Midori based on SPN structure is a lightweight block cipher developed to optimize energy consumption for resource-constrained environments.In this paper,the encryption structure of the Midori64 algorithm is optimized,and a kind of new iteration-based hardware architecture is proposed to optimize the area of Midori64 encryption and improve the reuse rate of components.In this structure,the whitening key addition and the round key addition are integrated,and the whitening key addition or the round key addition is transformed by a multiplexer.The experimental results show that the resource area occupied by the Midori64 encryption algorithm based on the new hardware architecture is reduced by 100 LUTS,the optimization efficiency is up to 26.25%,and the hardware realization area is effectively saved.At the same time,the encryption speed of which increased by 20.53 percent and the energy consumption of which decreased by 17.15 percent.