基于毛刺阻塞原理的低功耗双边沿触发器

A Low Power DETFF with Glitch Resistant Capability

当输入信号存在毛刺时,双边沿触发器的功耗通常会显著增大,为了有效降低功耗,提出一种基于毛刺阻塞原理的低功耗双边沿触发器。在该双边沿触发器中,采用了钟控CMOS技术C单元。一方面,C单元能有效阻塞输入信号存在的毛刺,防止触发器锁存错误的逻辑值。另一方面,钟控CMOS技术可以降低晶体管的充放电频率,进而降低电路功耗。相比其他现有双边沿触发器,该双边沿触发器在时钟边沿只翻转一次,大幅度减少了毛刺引起的节点冗余跳变,有效降低了功耗。与其他5种双边沿触发器相比,该双边沿触发器的总功耗平均降低了40.87%~72.60%,在有毛刺的情况下,总功耗平均降低了70.10%~70.29%,仅增加22.95%的平均面积开销和5.97%~6.81%的平均延迟开销。

According to the problem that the power consumption of most existing double edge-triggered flip-flops(DETFF)will increase significantly when there are glitches in the input data,a new type of low power DETFF with glitch resistant capability was proposed.The new DETFF used the C-elements with the clock-gating technology.On the one hand,the C-element had the function of filtering input glitches,which could effectively mask the glitches of the input data and reduce the impact of input glitches on the circuit.On the other hand,the clock-gating technology could reduce the charge and discharge frequency of the transistor to reduce the power consumption.Compared with other existing DETFFs,the proposed DETFF only flipped once on the clock edge,which greatly reduced the node redundancy transitions caused by the glitches and effectively reduced the power consumption overhead.Compared with the other five kinds of DETFFs,the total power consumption of the proposed one was reduced by 40.87%~72.60%on average,and the total power consumption with glitches was reduced by 70.10%~70.29%on average,which only increased the average area overhead by 22.95%and the average delay overhead by 5.97%~6.81%.