复杂电网环境下基于DDM-QT1-PLL的并网同步方法

Grid-connected synchronization method based on DDM-QT1-PLL under complex grid conditions

随着分布式电源并网的增加,电网面临着电压扰动、直流偏置、电压不平衡及谐波畸变等诸多问题。在这样的复杂电网环境下,传统锁相环技术(PLL)难以快速、准确地检测到电网电压的频率和相位。为此,提出在准1型锁相环(QT1-PLL)的结构中额外增加联合延时信号消除(DSC)和滑动平均滤波器(MAF)的滤波环节,设计出一种满足复杂电网环境下并网需求的新型PLL(DDM-QT1-PLL)。DDM-QT1-PLL采用αβDSC2与dqDSC4级联MAF的环外滤波和环内滤波结构,消除电网电压直流偏置、不平衡及谐波分量的同时,可有效提高PLL系统的响应速度和稳定性。针对频率偏移时,αβDSC2引起的相位误差,设计一种前馈通道以补偿误差。仿真结果表明DDM-QT1-PLL具有快速的响应速度和良好的干扰抑制能力,并能够在非额定频率的直流偏置下,实现检测频率和相位的零稳态误差。

With the increase of the distributed power grid-connected,the grid is facing many problems,such as voltage disturbance,DC offset,unbalanced voltage,harmonic distortion and so on.The traditional Phase-Locked Loop(PLL)technique finds it hard to detect the frequency and phase of grid voltage quickly and accurately under such complex grid conditions.To this end,a new PLL(DDM-QT1-PLL)is proposed,adding additional filtering stages consisting of Delay Signal Cancelation(DSC)and Moving Average Filter(MAF)into the Quasi-Type-1 PLL(QT1-PLL).It is constructed to meet the grid-connected demand in complex grid conditions.αβDSC2 and dqDSC4 cascaded MAF are adopted as the out-loop and in-loop filtering in DDM-QT1-PLL to eliminate grid voltage DC offset,unbalanced and harmonic components,as well as to effectively improve the response speed and stability margin of the PLL system.A feed forward path is designed to compensate the phase error caused byαβDSC2 when the grid frequency drifts.Simulation results show that DDM-QT1-PLL has a fast response speed and provides a good disturbance rejection capability,and achieves a zero steady-state error under DC offset of non-nominal frequency.