高性能模数变换器测试平台设计

Design of Test Platform for High Performance Analog-to-digital Converter Measurement

雷达和通信系统中使用的模数变换器(analog-to-digital converter, ADC)的带宽和采样率越来越高,接口形式从并口向JESD204B发展。为了满足ADC芯片在开发、生产、评估和应用中进行性能测试的需求,在研究ADC性能指标及其测试方法的基础上,采用高性能可编程逻辑门阵列(field-programmable gate array, FPGA)结合DSP(digital signal processor)的架构,设计了通用的高性能模数变换器性能测试平台,开发了数据采集和性能分析软件,并且针对多款不同接口形式且采样率从240 MSPS(million samples per second)到5 GSPS(gigabit samples per second)的ADC进行了性能测试实验。结果表明,该平台能够满足最新ADC的性能测试需求,具有接口灵活、运算能力强、实时性高等特点。

Bandwidth and sampling rate of the analog-to-digital converters(ADCs) used in radar and communication systems are becoming higher and higher. Meanwhile ADC interfaces are developed from parallel ports to serial JESD204 B. In order to meet the performance test requirements of ADC chips in design, manufacturing, sample evaluating and application, a test platform for high speed ADCs was designed after the ADC specifications and the test methods investigated. The test platform was based on an architecture constructed of high-performance field-programmable gate array(FPGA) and digital signal processor(DSP), with the data capturing and performance analysis software developed. Experiments were carried out with multiple types of ADCs on the proposed platform. These ADCs are in different types of interfaces and in sampling rates ranging from 240 million samples per second(MSPS) to 5 gigabit samples per second(GSPS). The results show that the proposed platform is characterized by flexible interface, strong computing ability and high real-time processing, and it can achieve the performance measurement of the newest ADCs.