基于FPGA的SDD探测器随机信号模拟发生器

A random signal emulator for silicon drift detector based FPGA

设计了一款硅漂移探测器(Silicon Drift Detector,SDD)信号模拟器用于测试SDD读出电子学的性能。该信号模拟器采用现场可编程门阵列(Field Programmable Gate Array,FPGA)作为核心器件,利用其丰富的可编程逻辑资源产生多组振荡环,将其输出相异或生成均匀分布的真随机数。首先通过伯努利试验将均匀分布的随机数转化为时间间隔服从指数分布的脉冲序列,然后对随机数进行了美国国家标准与技术研究院(National Institute of Standards and Technology,NIST)随机性测试,最后测试了信号模拟器输出脉冲的时间间隔和计数率特性,结果表明:SDD信号模拟器的输出脉冲时间间隔服从指数分布、输出计数率范围为1.6~813.8 ks^-1、输出脉冲的电压范围为2.5~50 mV、脉冲最小时间间隔为9.6 ns,并且可长时间稳定工作。

[Background] The enhanced X-ray Timing and Polarimetry mission(eXTP) is a space science mission designed to study fundamental physics under extreme conditions of density, gravity and magnetism. The spectroscopic focusing array(SFA) is one of eXTP’s four payloads, and its main function is to achieve spectrum and timing measurements with high dynamic range and high signal-to-noise ratio(SNR). The SFA uses multi-pixel silicon drift detector(SDD) as the focal plane detector. [Purpose] This study aims to design an SDD signal emulator for the performance test of SFA readout electronics. [Methods] The field programmable gate array(FPGA) was used as the core device of this emulator, making use of its abundant programmable logic resources to generate multiple groups of oscillatory loops. First of all, the configurable logic blocks inside the FPGA were designed as multiple oscillating rings, and its outputs were XOR-ed as true random numbers generator(TRNG). By Bernoulli trials, the uniform random numbers were converted into exponential pulse sequence. Then, the NIST(National Institute of Standards and Technology) suite was employed to test the quality of the TRNG output. Finally, the time interval distribution and counting rate characteristic of output pulses for the emulator were tested. [Results] The sequence of true random numbers of 1 000 Mbits have passed the NIST randomness test. The time interval of the output pulses for the emulator follows the exponential distribution. The dynamic range of counting rate is 1.6 ks^-1 to 813.8 ks^-1. The voltage range of the output pulse is 2.5 mV to 50 mV, and the minimum time interval is 9.6 ns. The signal emulator can work steadily for a long time. [Conclusions] The SDD signal emulator proposed in this paper can meet the requirements of performance tests for the SFA readout electronics.