数字芯片有效门限电压延时的分析及创新实验

Analysis and innovation experiment of effective threshold voltage delay of digital chip

实际数字芯片中引起各管脚响应的电压存在差异,即各管脚的有效门限电压不一致,造成当同一信号同时输入芯片不同管脚时,各管脚响应不同步,后响应的相较于先响应的存在延时,这就是数字芯片有效门限电压延时。现有理论教材及仿真软件皆未考虑此类延时,但该客观存在的延时可简化电路设计及实现创新性实验。

In actual digital chips,there is a difference in the voltages that cause the response of each pin,that is,the effective threshold voltage of each pin is inconsistent,resulting in when the same signal is input to different pins of the chip at the same time.The response of each pin is not synchronized,compared to the first response after the existence of the response delay,what is the chip effective threshold voltage delay.Existing theory and simulation software are not considered such a delay,but the objective existence of delay can simplify the circuit design and implement innovative experiment.