基于UVM实现SM4算法的自动化验证平台

UVM-based Automatic Verification Platform for SM4 Algorithm

在轨道交通安全通信系统中,为提升系统性能并降低软件复杂度,CPLD/FPGA和定制芯片等硬件产品得到广泛应用,逻辑功能仿真验证是保证上述硬件产品质量的重要环节。以SM4加解密算法模块为验证对象,采用SystemVerilog语言构建基于UVM的自动化验证平台。区别于传统的验证方法,该平台采用随机测试向量并利用DPI接口内嵌C函数模型,实现仿真数据自动化实时监控,避免单纯用人工检查,有效提高仿真验证效率。

In rail transit safety communication system,in order to improve system performance and reduce complexity of the software,widely use hardware products such as CPLD/FPGA and custom chips,simulation verification for logic function is an important link to ensure the quality of above hardware products.This paper takes SM4 encryption and decryption algorithm module as verification object,and uses SystemVerilog language construction based on UVM automatic verification platform.Different from traditional verification methods,the platform uses random test vectors and contains embedded the model of Function C by the use of DPI interface,to realize real-time monitoring of simulation data,in order to avoid manual inspection and improve the efficiency of simulation verification.