基于LVDS的并行高速AD接口逻辑设计与实现

Parallel High-speed AD Interface Logic Design and Implementation Based on LVDS

随着高速AD在电子测量、宽带通信等领域的广泛应用,FPGA与高速AD的接口设计成为关键和难点,其性能影响应用功能的实现。基于FPGA驱动,实现了LVDS并行ADC配置方案以及时钟数据的时序同步;采用Xilinx XC7A200T芯片和HMCAD1520 AD芯片,实现了250 Msps×14 Bit×2通道的采集设计。逻辑仿真结果验证了设计的合理性,实际板卡测试正确。该系统接口逻辑简单,通用扩展性强,可为并行LVDS驱动高速AD数据采集设计提供有效可行的参考。

With the wide application of high-speed AD in the fields including electronic measurement and broadband communication,the interface design of FPGA and high-speed AD has become a key and difficult point,and its performance affects the realization of application functions.Based on the FPGA driver,the LVDS parallel ADC configuration scheme and timing synchronization of clock data are realized.Xilinx XC7A200T chip and HMCAD1520 AD chip are used,so that 250 Msps×14 Bit×2 Channel acquisition design is realized.The logic simulation results verify the rationality of the design,and the actual board test is correct.Such a system has simple interface logic and strong universal scalability,which can provide effective and feasible references for the design of parallel LVDS driven high-speed AD data acquisition.