FPGA高速串行收发器时钟同步设计

The Design of Clock Synchronization for High Speed Serial Transceivers Inside FPGA

在为粒子加速器设计定时系统时,通常采用集成高速串行收发器的FPGA来实现。为了消除串行收发器恢复时钟相位的不确定性,本设计利用串行收发器接收端恢复数据检测时钟相位,然后采用"重启法"实现恢复时钟相位的固定。该方法不需要额外的硬件设计,只使用一路串行收发器和少量硬件语言编程,简单易行,并经过了实验室验证。

When designing timing systems for particle accelerators,FPGA integrated with high-speed serial transceiver is usually used.In order to eliminate the uncertainty of the phase of recovered clock,a method of detecting the clock phase using the recovered data is designed,and then the"reset method"is adopted to achieve the stabilization of the recovered phase.This method does not require additional hardware,only use one serial transceiver and a small number of hardware language programming statements,simple and easy,and has been verified in the laboratory.