一种串口数据帧拼接现象处理研究

Research and Processing of Serial Interrupt Data Frame Splicing

在某型以FPGA+C8051单片机架构的控制模块内,采用串行通信总线RS232实现FPGA与单片机之间的数据交互;为实现单片机因外部高优先级的中断触发串口接收中断关闭,导致串口接收再次打开后,出现数据帧错位、数据帧拼接现象的异常问题;对单片机接收一帧完整的数据帧时长、接收一帧数据的处理机制、接收数据帧拼接的机制等进行研究处理,并在程序内设置监测点对串口数据帧被外部中断触发中断的关闭时长、中断发生的频次等进行监测;证实了此次串口数据帧拼接、数据帧错误问题引起的因素为单片机串口接收开启后,受到外部高优先级中断触发串口中断关闭,在执行高优先级中断的同时,FPGA控制软件端并未停止串口数据帧的发送,在单片机串口中断重新开启后,新的串口数据帧与单片机关闭中断前接收的部分数据帧进行拼接,出现数据帧拼接异常现象;且在拼接数据帧中含有与通信协议中数据帧帧尾一致的数据时,该帧数据就会被判读为正常数据帧,从而出现数据解析时,数据帧有拼接、错位的异常问题;采用在通信数据错位异常的软件中增加监测信号及相应的测试用例对串口接收中断关闭时间捕获,实现了对串口数据帧拼接的结果分析和试验验证;对通信数据错位异常采取减小串口中断关闭时间等更改措施后,确保了串口数据帧接收时,因串口关闭时间过长而导致的通信数据拼接、错位的异常现象;有效地解决了因串口关闭时间过长导致的数据拼接问题,保证了该控制模块的FPGA与单片机之间通信数据的正常。

In a certain type of control module based on FPGA + C8051 single-chip microcomputer architecture,serial communication bus RS232 is used to realize data interaction between FPGA and single-chip microcomputer.In order to realize the abnormal solution of the single-chip computer due to the external high-priority interrupt triggering the serial port receiving interrupt to close,resulting in the serial port receiving being opened again,the data frame is misaligned and the data frame is spliced.Research and process the duration of a complete data frame received by the microcontroller,the processing mechanism of receiving a frame of data,the mechanism of receiving data frames,etc.,and set the monitoring point in the program to close the serial data frame by an external interrupt.The frequency of interrupt occurrence is monitored;it is confirmed that the factors caused by this serial data frame splicing and data frame error problem are that after the serial port reception of the microcontroller is turned on,the external high-priority interrupt is triggered to close the serial port interrupt.The FPGA control software does not stop the serial data frame transmission.After the serial port interruption of the microcontroller is restarted,the new serial data frame is spliced??with some of the data frames received before the interruption of the microcontroller is turned off.When the data frame contains data that is consistent with the end of the data frame in the communication protocol,the frame data will be interpreted as a normal data frame,so that there is an abnormal problem of splicing and misalignment during data analysis.The monitoring signal and the corresponding test case are added to the software with abnormal communication data misalignment to capture the serial port interruption off time capture,and the result analysis and experimental verification of the serial data frame splicing are realized.After taking measures such as reducing the serial port interruption closing time for the abnormal communication data misplacement,it ensures the abnormal phenomenon of splicing and misalignment of the communication data caused by the serial port closing time when the serial data frame is received.It effectively solves the problem of data splicing caused by the serial port closing time being too long,and ensures the normal communication data between the FPGA and the single chip of the control module.