面向移动终端的残差网络加速器设计

Design of Residual Network Accelerator for Mobile Terminals

残差网络(Residual Network,Res Net)因在图像分类、对象检测等领域中表现出优异的成绩而被广泛应用.但是由于Res Net模型结构的高度不规则和复杂度,使得其在移动终端的部署仍是一个具有挑战性的工作.本文设计一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)的残差网络硬件加速器.首先,采用k-means聚类算法对网络参数进行量化,降低参数的存储需求.其次,通过流水线和并行计算策略实现各计算单元的加速计算,并通过残差计算单元的复用降低对计算资源的需求.所提出的加速器能够有效地在Zynq-ZCU102上实现Res Net,其系统时钟可达到300MHz,延时为26.47ms,DSP占用率为60.4%,LUTRAM占用率为4%.

The Residual Network(Res Net)is widely used for its excellent performance in image classification and object detection.However,due to the high degree of irregularity and complexity of the model structure,deploying the Res Net on mobile terminals is still a challenging task.In this paper,a Res Net accelerator based on Field Programmable Gate Array(FPGA)is designed.Firstly,the kmeans clustering algorithm is used to quantify the network parameters in order to reduce the storage requirements of the parameters.Secondly,each computing unit is implemented through pipeline and parallel computing.And reusing the unit of residual calculation reduces the requirement of computing resources.The proposed hardware accelerator can efficiently deploye the Res Net on Zynq-ZCU102 FPGA with 300 MHz of clock frequency and 26.43 ms of latency.The occupancy rates of the DSP and LUTRAMare 60.4%and 4%,respectively.