一种快速锁定低抖动的时钟数据恢复电路

A Fast Locking and Low Jitter Clock and Data Recovery Circuit

设计了一款应用于光通信28 Gb/s非归零码高速串行接收机的快速锁定、低抖动时钟数据恢复电路。为了解决时钟抖动性能和锁定时间难以兼顾的问题,在比例-积分通路分离的电路结构中,提出了锁定检测判别技术,实现了比例通路增益的可调节,使得环路能够在低抖动的情况下快速锁定。通过Cadence Spectre进行仿真,当环路中使用锁定检测判别技术时,锁定时间为400 ns,抖动峰峰值为2.5 ps。相较于未使用该技术的环路,锁定时间缩短了33%,抖动降低了40%。

This paper designs a fast locking and low jitter clock and data recovery circuit applied to 28 Gb/s non-return-to-zero code high-speed serial optical communication receiver.In order to solve the problem that clock jitter and locking time are difficult to be considered at the same time,the lock detection and discrimination technology is proposed in the circuit with separate proportional-integral path to realize the adjustable gain of proportional path and enable the loop to lock quickly under condition of low jitter.The simulation is carried out by Cadence Spectre.When the lock detection and discrimination technology is used in the loop,the locking time is about 400 ns and the jitter peak-to-peak value is about 2.5 ps.Compared with the other two schemes,the locking time is reduced by 33%and the jitter is reduced by 43%.